? semiconductor components industries, llc, 2005 july, 2005 ? rev. 9 1 publication order number: mc74hc540a/d mc74hc540a octal 3?state inverting buffer/line driver/line receiver high?performance silicon?gate cmos the mc74hc540a is identical in pinout to the ls540. the device inputs are compatible with standard cmos outputs. external pull?up resistors make them compatible with lsttl outputs. the hc540a is an octal inverting buffer/line driver/line receiver designed to be used with 3?state memory address drivers, clock drivers, and other bus?oriented systems. this device features inputs and outputs on opposite sides of the package and two anded active?low output enables. the hc540a is similar in function to the hc541a, which has noninverting outputs. features ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with the jedec standard no. 7a requirements ? chip complexity: 124 fets or 31 equivalent gates ? pb?free packages are available* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com 20 1 1 20 marking diagrams soic?20 dw suffix case 751d 74hc540a awlyywwg hc 540a alyw tssop?20 dt suffix case 948e soeiaj?20 f suffix case 967 74hc540a awlywwg 1 1 1 20 1 20 20 20 see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information pdip?20 n suffix case 738 1 20 mc74hc540an awlyywwg 1 2 0 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free package = pb?free package (note: microdot may be in either location)
mc74hc540a http://onsemi.com 2 figure 1. pinout: 20?lead packages (top view) 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 oe2 y1 y2 y3 y4 y5 y6 y7 y8 oe1 a1 a2 a3 a4 a5 a6 a7 a8 gnd l l h x l l x h l h x x function table inputs output y oe1 oe2 a h l z z z = high impedance x = don?t care figure 2. logic diagram 18 y1 2 a1 17 y2 3 a2 16 y3 4 a3 15 y4 5 a4 14 y5 6 a5 13 y6 7 a6 12 y7 8 a7 11 y8 9 a8 oe1 oe2 1 19 output enables data inputs inverting outputs pin 20 = v cc pin 10 = gnd ordering information device package shipping ? mc74hc540an pdip?20 18 units / rail mc74hc540ang pdip?20 (pb?free) 18 units / rail mc74hc540adw soic?20 wide 38 units / rail MC74HC540ADWG soic?20 wide (pb?free) 38 units / rail mc74hc540adwr2 soic?20 wide 1000 tape & reel mc74hc540adwr2g soic?20 wide (pb?free) 1000 tape & reel mc74hc540adtr2 tssop?20* 2500 tape & reel mc74hc540adtr2g tssop?20* 2500 tape & reel mc74hc540af soeiaj?20 40 units / rail mc74hc540afg soeiaj?20 (pb?free) 40 units / rail mc74hc540afel soeiaj?20 2000 tape & reel mc74hc540afelg soeiaj?20 (pb?free) 2000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free.
mc74hc540a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to v cc 0.5 v v o dc output voltage (note 1) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 35 ma i o dc output sink current 35 ma i cc dc supply current per supply pin 75 ma i gnd dc ground current per ground pin 75 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance pdip soic tssop 67 96 128 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) 2000 200 1000 v i latchup latchup performance above v cc and below gnd at 85 c (note 5) 300 ma maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. i o absolute maximum rating must be observed. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to jesd22?c101?a. 5. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit ???? ???? v cc ????????????????????? ????????????????????? ????? ????? ???? ???? ??? ??? ???? ???? ????????????????????? ????????????????????? ????? ????? ???? ???? ??? ??? ???? ???? ????????????????????? ????????????????????? ????? ????? 55 ???? ???? 125 ??? ??? c ???? ? ?? ? ???? t r , t f ????????????????????? ? ??????????????????? ? ????????????????????? input rise and fall time (figure 3) v cc = 2.0 v v cc = 4.5 v v cc = 6.0 v ????? ? ??? ? ????? 0 0 0 ???? ? ?? ? ???? 1000 500 400 ??? ? ? ? ??? ns 6. unused inputs may not be left open. all inputs must be tied to a high? or low?logic input voltage level.
mc74hc540a http://onsemi.com 4 dc characteristics (voltages referenced to gnd) v cc v guaranteed limit symbol parameter condition ?55 to 25 c 85 c 125 c unit v ih minimum high?level input voltage v out = 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum low?level input voltage v out = v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v oh minimum high?level output voltage v in = v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v il |i out | 3.6 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum low?level output voltage v in = v ih |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih |i out | 3.6 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i oz maximum three?state leakage current output in high impedance state v in = v il or v ih v out = v cc or gnd 6.0 0.5 5.0 10.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a 7. information on typical parametric values can be found in the on semic onductor high?speed cmos data book (dl129/d). ac characteristics (c l = 50 pf, input t r = t f = 6 ns) v cc v guaranteed limit symbol parameter ?55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a to output y (figures 3 and 5) 2.0 3.0 4.5 6.0 80 30 18 15 100 40 23 20 120 55 28 25 ns t plz , t phz maximum propagation delay, output enable to output y (figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns t pzl , t pzh maximum propagation delay, output enable to output y (figures 4 and 6) 2.0 3.0 4.5 6.0 110 45 25 21 140 60 31 26 165 75 38 31 ns t tlh , t thl maximum output transition time, any output (figures 3 and 5) 2.0 3.0 4.5 6.0 60 22 12 10 75 28 15 13 90 34 18 15 ns c in maximum input capacitance 10 10 10 pf c out maximum 3?state output capacitance (output in high impedance state) 15 15 15 pf 8. for propagation delays with loads other than 50 pf, and information on typical parametric values, see the on semic onductor high?speed cmos data book (dl129/d). c pd power dissipation capacitance (per buffer) (note 9) typical @ 25 c, v cc = 5.0 v, v ee = 0 v pf 35 9. used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see the on semiconductor high?speed cmos data book (dl129/d).
mc74hc540a http://onsemi.com 5 figure 3. switching waveform v cc gnd input a output y t phl oe1 or oe2 50% v cc gnd output y t pzl output y t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% t plh 90% 50% 10% t r t thl t f t tlh figure 4. switching waveform 90% 50% 10% 50% c l * *includes all probe and jig capacitance test point device under test output figure 5. test circuit figure 6. test circuit c l * *includes all probe and jig capacitance test point device under test output 1k connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . figure 7. logic detail one of eight inverters input a oe1 oe2 output y v cc to 7 other inverters pin descriptions inputs a1, a2, a3, a4, a5, a6, a7, a8 (pins 2, 3, 4, 5, 6, 7, 8, 9) data input pins. data on these pins appear in inverted form on the corresponding y outputs, when the outputs are enabled. controls oe1, oe2 (pins 1, 19) output enables (active?low). when a low voltage is applied to both of these pins, the outputs are enabled and the device functions as an inverter. when a high voltage is applied to either input, the outputs assume the high impedance state. outputs y1, y2, y3, y4, y5, y6, y7, y8 (pins 18, 17, 16, 15, 14, 13, 12, 11) device outputs. depending upon the state of the output enable pins, these outputs are either inverting outputs or high?impedance outputs.
mc74hc540a http://onsemi.com 6 package dimensions pdip?20 n suffix plastic dip package case 738?03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 ?a? seating plane k n f g d 20 pl ?t? m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc soic?20 dw suffix case 751d?05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc74hc540a http://onsemi.com 7 package dimensions tssop?20 dt suffix case 948e?02 issue b dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. 110 11 20 pin 1 ident a b ?t? 0.100 (0.004) c d g h section n?n k k1 jj1 n n m f ?w? seating plane ?v? ?u? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 ??? ??? s u 0.15 (0.006) t
mc74hc540a http://onsemi.com 8 package dimensions soeiaj?20 f suffix case 967?01 issue o dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 12.35 12.80 0.486 0.504 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 0.81 ??? 0.032 a 1 h e q 1 l e 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). h e a 1 l e q 1 c a z d e 20 110 11 b m 0.13 (0.005) e 0.10 (0.004) view p detail p m l a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc74hc540a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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